1. Field of the Invention
The invention generally relates to computer display systems; and in particular, the present invention relates to a display controller supporting multiple overlays on a computer display.
2. Background of the Invention
A graphics display system of a personal computer must support a complex video display including multiple windows of text, graphical data and movie images. FIG. 1 is a block diagram of a typical graphics display system 100. System 100 includes display controller 101, system processor 102 and memory interface 103, all communicating over a system bus 106. System 100 further includes frame buffer memory 104 which is depicted here as including frame buffers 104a, 104b, and 104c and coupled to system bus 106 through memory interface 103. Frame buffer memory 104 typically has the capacity to store pixel data for at least one frame of a video display image. Video images are generally represented as sequences of frames where each frame is a matrix of pixels that vary in color and intensity according to the image displayed.
Display controller 101 and system processor 102 access frame buffer memory 104 via system bus 106. System processor 102 stores video data, or pixel data, for each frame of video image in frame buffer memory 104. Display controller 101 retrieves the stored video data and processes the data to generate graphics commands and data for driving a computer display 105. Graphics display system 100 is intended to be representative of those used in conventional general purpose personal computers and elements of system 100 are illustrative of those found in most personal computers.
Computer display 105 is a raster display monitor and display video images based on graphics commands and data generated by display controller 101. Display 105 can be any cathode ray tube (CRT) monitor or raster display monitor. Display 105 can also be any liquid crystal display (LCD) monitor. Display 105 displays a screen of image by scanning each line of pixel data horizontally, starting from the upper-left corner. After completing scanning a field of image (i.e. a full screen), the scan beams return to the upper-left corner to begin scanning and displaying the next field of pixel data. In general, the fields of pixel data are scanned on display 105 at a standardized display rate in the range of 60 to 85 frames/sec. Display controller 101 generates sync signals to align the display data with the scan beams. Typically, display controller 101 issues a vertical sync signal at the beginning of each display field (i.e. the upper-left corner of display 105) and a horizontal sync signal at the beginning of each scan line.
To compose a field of pixel data, display controller 101 accesses pixel data stored in frame buffers 104a-c for processing. When a video image includes multiple overlays, display controller 101 initiates a single control thread to process the pixel data for the video image. The control thread generates graphics commands and data, hereinafter cumulatively called display signals, for all the overlays within the frame of video image. Because only one control thread is used to process pixel data for all of the overlays, display controller 101 processes pixel data for each overlay in a lock-step fashion. Display controller 101 has poor memory latency tolerance because the processing of pixel data is limited by the slowest process required for a particular overlay. The latency in processing can cause the display image to suffer the effect of tearing or rolling.
It would be desirable to provide a display controller capable of processing pixel data at an improved rate so that the computer display can transition seamlessly between each frame of display images, thereby eliminating image tearing or rolling.